Stripline PCB Differential Impedance Calculator
Estimate the differential impedance of a stripline pair on a multilayer PCB. Enter the single-ended impedance, trace spacing, and height to the reference plane to get Z_diff in ohms.
Differential Pair Impedance in Stripline Geometry
Stripline Differential Impedance Formula
Where:
- \( Z_{\text{diff}} \) — differential impedance of the pair (Ω)
- \( Z_0 \) — single-ended characteristic impedance of one stripline trace (Ω)
- \( s \) — spacing between the centers of the two traces of the pair
- \( h \) — distance from the trace to the reference plane (same units as \( s \))
Only the ratio \( s/h \) matters, so spacing and height can be entered in any consistent unit (mm, mil, µm). This empirical model applies to symmetric stripline: two identical traces embedded between two reference planes, with equal dielectric above and below the trace. The coupling term \( 1 - 0.347 e^{-2.9s/h} \) shows that tighter coupling (smaller spacing relative to height) lowers the differential impedance below the uncoupled value of \( 2Z_0 \).
Stripline Differential Impedance – Calculation Example
Example: a 50 Ω stripline pair is routed on an inner layer of a multilayer board. The traces are 0.2 mm apart, and each trace sits 0.2 mm from the nearest reference plane.
\[ \frac{s}{h} = \frac{0.2}{0.2} = 1 \]
\[ e^{-2.9 \cdot 1} \approx 0.0550 \]
\[ Z_{\text{diff}} = 2 \cdot 50 \cdot \left( 1 - 0.347 \cdot 0.0550 \right) = 100 \cdot 0.9809 \approx 98.09~\Omega \]
Result: the differential impedance is approximately 98.09 Ω — close to, but slightly below, the 100 Ω you would get from two completely uncoupled 50 Ω traces.
How to Use the Calculator
- Enter the Single-Ended Impedance of one trace of the pair in ohms. If you do not know it yet, compute it first with the Stripline Impedance Calculator.
- Enter the Spacing Between Lines — the center-to-center distance between the two traces of the differential pair.
- Enter the Substrate Height — the distance from the trace to the adjacent reference plane (half the dielectric thickness between the two planes of a symmetric stripline).
- Read the Differential Impedance in ohms. Make sure spacing and height use the same unit; only their ratio enters the formula.
What Is Stripline Differential Impedance?
A stripline is a copper trace routed on an internal layer of a multilayer PCB, fully embedded in dielectric material and sandwiched between two reference (ground or power) planes. This construction gives stripline traces a homogeneous environment, predictable characteristic impedance, and better immunity to electromagnetic interference than surface traces — at the cost of harder routing and debugging.
A differential pair is two matched traces that carry one signal as the voltage difference between them. Interfaces such as USB, HDMI, PCIe, LVDS, and gigabit Ethernet rely on differential signaling because it rejects common-mode noise and reduces electromagnetic emissions. Each of these standards specifies a target differential impedance — commonly 90 Ω (USB), 100 Ω (Ethernet, PCIe, LVDS), or 85 Ω for some high-speed variants — and both the driver and receiver are designed to match it.
The differential impedance of a pair is not simply twice the single-ended impedance. Because the two traces are physically close, they are capacitively and inductively coupled. This coupling makes the differential impedance lower than \( 2Z_0 \), and the effect strengthens as the spacing \( s \) shrinks relative to the height \( h \). When the traces are far apart (\( s/h \gg 1 \)), the coupling term vanishes and \( Z_{\text{diff}} \to 2Z_0 \). When they are tightly coupled, the pair can drop several ohms below \( 2Z_0 \) — the example above shows a 50 Ω pair settling near 98 Ω instead of 100 Ω.
Matching the differential impedance to the target matters because any discontinuity — a wrong impedance segment, a via, a break in the reference plane — reflects part of the signal energy. Reflections cause overshoot, ringing, jitter, and eye-diagram closure, which at multi-gigabit data rates translate directly into bit errors. Designers typically aim to hit the target impedance within about ±10% along the entire route.
Assumptions, Limitations and Practical Tips
- Symmetric stripline only. The formula assumes identical traces placed symmetrically between two reference planes with uniform dielectric. It does not apply to microstrip (outer-layer) traces or asymmetric (dual-stripline) stackups.
- Empirical accuracy. The expression is a closed-form approximation. Expect results within roughly ±5% of full 2D field-solver values for typical geometries. For production designs, always verify with a field solver or controlled-impedance stackup tool from your PCB fabricator.
- Wide spacing decouples the pair. With \( s/h \) above about 3, the coupling term is negligible and the answer is essentially \( 2Z_0 \). In that regime, focus your tuning effort on the single-ended impedance.
- Tight coupling lowers impedance. If the calculated value is too high, reduce the spacing between the traces; if it is too low, increase the spacing or adjust the trace geometry so \( Z_0 \) rises.
- Keep the pair symmetric along the route. Maintain equal trace lengths, identical layer usage, and a continuous reference plane under the entire pair. Avoid routing other signals between the two traces of the pair, and keep unrelated aggressor traces away to limit crosstalk — see the PCB Microstrip Crosstalk Calculator for evaluating that coupling.
- Units must be consistent. The calculator only uses the ratio \( s/h \), so mixing mm and mil between the two fields is a common source of large errors.
- Connector and termination matching. When the source or load needs a matching network to bridge impedance levels, the PI Network Impedance Matching Calculator can help design it.
Quick Reference: Coupling vs. Differential Impedance
| Spacing-to-height ratio \( s/h \) | Coupling factor \( 0.347e^{-2.9s/h} \) | \( Z_{\text{diff}} \) for \( Z_0 = 50\ \Omega \) |
|---|---|---|
| 0.5 | 0.0829 | 91.71 Ω |
| 1.0 | 0.0191 | 98.09 Ω |
| 2.0 | 0.0010 | 99.90 Ω |
| 3.0 | ≈ 0.00005 | ≈ 100 Ω |
The table shows how quickly the pair decouples: beyond \( s/h = 2 \), the differential impedance is within 0.1% of \( 2Z_0 \), and further spacing changes provide no measurable benefit.
Frequently Asked Questions
How do I calculate stripline differential impedance by hand?
Take the single-ended impedance \( Z_0 \) of one trace and apply \( Z_{\text{diff}} = 2Z_0 (1 - 0.347 e^{-2.9s/h}) \). Divide the center-to-center spacing by the height to the reference plane, raise \( e \) to the power \( -2.9 \times s/h \), multiply by 0.347, subtract from 1, then multiply by \( 2Z_0 \). For s/h = 1 and \( Z_0 = 50\ \Omega \), you get about 98.1 Ω.
Can I enter spacing in mm and height in mils?
No. Only the ratio \( s/h \) enters the formula, so both fields must use the same unit. Mixing mm and mil is a common mistake: 1 mil equals 0.0254 mm, so a unit mismatch silently distorts the ratio by a factor of about 39 and produces wildly wrong results. Convert first, or use the same unit for both inputs — mm, mil, and µm all work as long as they are consistent.
Why is the differential impedance less than twice the single-ended impedance?
Two nearby traces couple capacitively and inductively. In a stripline pair the mutual capacitance between traces adds to the capacitance each trace sees, which lowers the odd-mode impedance of each line — and the differential impedance is twice the odd-mode value. As spacing grows relative to height, the coupling term \( 0.347e^{-2.9s/h} \) decays exponentially, and \( Z_{\text{diff}} \) approaches \( 2Z_0 \) (within 0.1% by \( s/h = 2 \)).
How accurate is this formula compared to a field solver?
It is a closed-form empirical approximation, typically accurate to within about ±5% of 2D field-solver results for common symmetric stripline geometries. Accuracy degrades for unusual cross-sections, very thin or very wide traces, or inhomogeneous dielectrics. For production boards, cross-check with your PCB fabricator's controlled-impedance stackup tool or a field solver, especially for multi-gigabit interfaces where reflections degrade signal margins.
What differential impedance targets do USB, HDMI, PCIe, and Ethernet require?
Common targets are 90 Ω for USB 2.0 and USB 3.x, 100 Ω for PCIe, gigabit Ethernet, and LVDS, and 85 Ω for some high-speed variants like certain HDMI and DDR interfaces. Always check the specific standard and your silicon datasheet. Designers generally aim to stay within about ±10% of the target along the whole route; larger deviations cause reflections, ringing, and eye-diagram closure.
Does this calculator work for microstrip traces on outer layers?
No. The model assumes symmetric stripline: identical traces embedded between two reference planes with uniform dielectric above and below. Outer-layer microstrip traces have air on one side, which changes both the single-ended impedance and the coupling behavior — microstrip coupling decays more slowly with spacing. For surface traces, use a microstrip differential impedance calculator instead.
My result is too high or too low — how do I tune the pair to hit the target?
If the calculated value is too high, tighten the coupling by decreasing the edge-to-edge spacing between the traces. If it is too low, increase the spacing or raise \( Z_0 \) by narrowing the traces, using a lower dielectric constant material, or moving the trace farther from the reference planes. Once \( s/h \) exceeds about 3, spacing no longer matters — tune \( Z_0 \) itself instead. Keep the pair symmetric along the entire route.
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