Microstrip PCB Differential Impedance Calculator
Estimate the differential impedance of an edge-coupled microstrip pair on a PCB by entering the single-ended impedance, trace spacing, and substrate height — essential for USB, HDMI, LVDS, and PCIe routing.
Differential Impedance Estimator for Microstrip Traces
Microstrip Differential Impedance Formula
Where:
- \(Z_{\text{diff}}\) — differential impedance of the pair (Ω)
- \(Z_0\) — single-ended impedance of one isolated microstrip trace (Ω)
- \(s\) — spacing between the two traces of the pair (mm)
- \(h\) — height of the dielectric substrate between the traces and the ground plane (mm)
This empirical expression describes a symmetrical, edge-coupled microstrip pair over a reference plane. As the traces move closer together (smaller \(s/h\)), the coupling between them increases and the differential impedance falls below twice the single-ended value.
Microstrip Differential Impedance – Calculation Example
Example: a pair of 50 Ω microstrip traces on a 1.6 mm thick substrate, spaced 0.15 mm apart.
\[ Z_{\text{diff}} = 2 \cdot 50 \cdot \left(1 - 0.48\,e^{-0.96 \cdot \frac{0.15}{1.6}}\right) \]
\[ = 100 \cdot \left(1 - 0.48\,e^{-0.09}\right) = 100 \cdot \left(1 - 0.48 \cdot 0.9139\right) \]
\[ = 100 \cdot 0.5613 \approx 56.13~\Omega \]
Result: the differential impedance of the pair is approximately 56.13 Ω.
How to use the calculator
- Enter the Single-ended impedance of one trace in ohms. If you do not know it yet, compute it first with the trace geometry using the Microstrip PCB Impedance calculator.
- Enter the Trace spacing \(s\) in mm — the edge-to-edge gap between the two traces of the pair.
- Enter the Substrate height \(h\) in mm — the distance from the trace layer to the reference ground plane.
- Read the Differential impedance result in ohms, shown to two decimal places.
What is microstrip differential impedance?
A differential pair carries one signal on two traces with equal and opposite voltages. The receiver responds only to the difference between the two lines, so the impedance that matters for termination and reflections is the differential impedance \(Z_{\text{diff}}\) — the impedance seen between the two traces of the pair.
For microstrips (traces on an outer layer, with air above and dielectric below the copper), the two traces of a pair couple to each other as well as to the ground plane. Because of this mutual coupling, the differential impedance is always less than \(2Z_0\). The tighter the spacing relative to the substrate height, the stronger the coupling and the lower the differential impedance. The formula used here captures that effect: at large spacing (\(s \gg h\)) the coupling term vanishes and \(Z_{\text{diff}} \to 2Z_0\), while tightly coupled pairs can land well below that value.
Getting this number right matters because most high-speed serial standards specify a differential impedance target — typically 90 Ω for USB 2.0/3.0, 100 Ω for Ethernet pairs, LVDS, PCIe, and many HDMI lanes. If the actual board impedance deviates from the target, part of the signal reflects at the receiver and driver, causing overshoot, ringing, jitter, and increased EMI. Poor impedance control is one of the most common causes of failed eye-diagram and return-loss tests.
Note that this calculator takes the single-ended impedance as an input rather than the trace width and dielectric constant. This makes it flexible: you can obtain \(Z_0\) from your stackup calculator, a field solver, or a measurement, then use this tool to see how a chosen spacing changes the pair impedance.
Assumptions, limitations, and practical tips
- Symmetrical pair. The formula assumes two identical traces of equal width, routed side by side at the same height above an unbroken ground plane. Asymmetric pairs behave differently and need a field solver.
- Edge coupling only. Only the lateral (edge-to-edge) coupling between the traces is modeled. Broadside-coupled pairs on adjacent layers are not covered.
- Empirical accuracy. This is a well-known closed-form approximation, accurate to a few percent for typical geometries. For final sign-off on gigabit-class designs, verify with a 2D field solver or an impedance test coupon.
- Choose spacing deliberately. Tight spacing lowers impedance and improves noise immunity, but it also increases insertion loss and crosstalk susceptibility to neighboring aggressors. To evaluate coupling to nearby traces, see the PCB Microstrip Crosstalk calculator.
- Common design workflow: pick a trace width for the target \(Z_0\), then tune the pair spacing until \(Z_{\text{diff}}\) matches the specification. Keep the spacing constant along the entire route and avoid vias and layer changes inside a pair whenever possible.
- Inner layers differ. If your differential pair runs on an inner layer between two reference planes, use the Stripline PCB Differential Impedance calculator instead, and the Stripline Impedance calculator for the single-ended value.
- Watch manufacturing tolerances. Etch-back, copper roughness, and dielectric thickness tolerance (±10% on prepreg is common) all shift the impedance. Design with margin, and confirm with a coupon if the spec is tight.
Frequently Asked Questions
Why is my differential impedance lower than 2 × single-ended impedance?
Because the two traces of a tightly spaced pair couple to each other. Each trace sees the neighbor's field, which lowers the odd-mode impedance of each line below its isolated value \(Z_0\), and \(Z_{\text{diff}} = 2Z_{\text{odd}}\). A common mistake is terminating a pair with \(2Z_0\); the actual value can be 10–20% lower, causing reflections. As spacing grows much larger than substrate height, coupling fades and the result approaches \(2Z_0\).
What differential impedance do USB, HDMI, PCIe, and Ethernet require?
Most standards target 90 Ω ±10% for USB 2.0 and USB 3.x, 100 Ω ±10% for PCIe, LVDS, and Ethernet pairs, and 100 Ω (some lanes 90 Ω) for HDMI. LVDS transmitters commonly specify 100 Ω. Always check your interface spec, as tolerances and odd-mode requirements vary. Design with margin toward the center of the allowed range to absorb manufacturing variation of ±10% or more on geometry.
How do I choose trace spacing to hit a 90 Ω or 100 Ω target?
Iterate: fix the trace width so the single-ended \(Z_0\) is around 50–55 Ω, then decrease the gap to lower the result or widen it to raise the result. Run the calculator with a few candidate spacings until \(Z_{\text{diff}}\) lands mid-range. Keep that exact spacing along the whole route — abrupt gap changes create impedance discontinuities and reflections, even if the average value looks correct.
Can I enter spacing and height in mils instead of mm?
The calculator expects millimeters, but only the ratio \(s/h\) matters in the formula — so any consistent unit gives the same answer. If both values are in mils (1 mil = 0.0254 mm), the result is identical. Mixing units, e.g. spacing in mm and height in mils, will silently give a wrong impedance, so double-check your stackup units before entering values.
Does soldermask or copper roughness change the result?
Yes, both are outside this model. Soldermask over the traces raises the effective dielectric constant near the copper and typically lowers the impedance by a few ohms; thicker mask drops it further. Copper roughness and etch-back change the effective trace width, and prepreg thickness tolerance of ±10% shifts \(h\) directly. For tight tolerances, derate your design or verify with a field solver and an impedance test coupon from the fab.
What is odd-mode impedance and how does it relate to this calculator?
Odd-mode impedance is the impedance of a single trace in a pair when both traces are driven with equal and opposite signals. The relationship is \(Z_{\text{diff}} = 2Z_{\text{odd}}\). You can divide this calculator's result by two to get \(Z_{\text{odd}}\), which matters when each line needs its own termination resistor to ground instead of a single resistor across the pair.
When does this formula break down or give inaccurate results?
It assumes a symmetrical pair, equal trace widths, a solid unbroken ground plane, and edge coupling only. It does not cover broadside-coupled pairs on adjacent layers, asymmetric widths, or traces crossing plane splits. Accuracy is typically within a few percent for ordinary geometries, but gigabit-class sign-off should be confirmed with a 2D field solver, since edge cases like gaps below ~0.1 mm or spacing larger than the trace width deviate more.